PCAP2
The PCAP2 is a Motorola ASIC that takes care of power management, sound, touchscreen and EMU. It is connected via SSP/SPI to both AP and BP.
It includes a number of linear and switching power regulators, taking care of the diverse voltage and power requirements of the various digital and analogue subsystems of the phone.
It also has the built-in microphone and speakers attached. Audio data is exchanged between PCAP2, AP, BP and the Bluetooth chip using SPI. It includes a Stereo DAC (for mp3 playing, ...) and a mono DAC for the voice audio.
Power management, Clock and Audio Peripheral
Features:
- produces a 16 different voltages
- handles all mono/stereo audio
- connected to 2 speakers, microphone, vibrator
- clock generation
- SPI/SSP interface to AP and BP
- Backlight control
Contents |
PCAP2 A780 register map
The PCAP2 has 32 25-bit registers which can be read and written via SPI. The PCAP2 has two different SPI busses (called primary and secondary). The primary SPI bus is connected to the baseband processor - the secondary is connected to the application processor. Some of the registers may only be written from the primary SPI bus. It is unknown if the registers accesed from the primary and secondary buses are the same or different sets.
The following registers are accessible only from the primary SPI bus and their location is unknown: VREG_MASK (cont
//The orgin version missed registors,all the registors can be found in include/linux/power_ic.h, and there is another almost same copy of the registers definition in drivers/misc/ssp_pcap.h,who knows what differences are between them and why to have 2 copies plz tell me(dotmonkey at gmail.com) :-)
| R | Name | Description |
|---|---|---|
| 0x00 | ISR | Interrupt status register |
| 0x01 | IMR | Interrupt mask register |
| 0x02 | PSTAT | Peripheral status register |
| 0x03 | INT_SEL | Interrupt select register |
| 0x04 | SWCTRL | Switching regulator control register |
| 0x05 | VREG1 | Regulator bank 1 control register |
| 0x06 | VREG2 | Regulator bank 2 control register |
| 0x07 | AUX_VREG | Auxiliary regulator control register |
| 0x08 | BATT_DAC | Battery control register |
| 0x09 | ADC1 | AtoD control register |
| 0x0a | ADC2 | AtoD result register |
| 0x0b | AUD_CODEC | Audio codec control register |
| 0x0c | AUD_RX_AMPS | Rx audio amplifiers control register |
| 0x0d | ST_DAC | Stereo DAC control register |
| 0x0e | RTC_TOD | Real Time Clock time of day register |
| 0x0f | RTC_TODA | RTC time of day alarm register |
| 0x10 | RTC_DAY | RTC day register |
| 0x11 | RTC_DAYA | RTC day alarm register |
| 0x12 | MTRTMR | AtoD monitor timer register |
| 0x13 | PWRCTRL | Power control register. |
| 0x14 | BUSCTRL | Connectivity register |
| 0x15 | PERIPH | Peripheral control register |
| 0x16 | AUX_VREG_MASK | Auxiliary regulator mask register |
| 0x17 | VENDOR_REV | |
| 0x18 | LOWPWR_CTRL | Regulator low power control register |
| 0x19 | PERIPH_MASK | Peripheral control register |
| 0x1a | TX_AUD_AMPS | Tx audio amplifiers control register |
| 0x1b | GP | General purpose register |
| 0x1c | TEST1 | |
| 0x1d | TEST2 | |
| 0x1e | VENDOR_TEST1 | |
| 0x1f | VENDOR_TEST2 |
VAUX2
On the E680 VAUX2 is connected to SD/MMC card power. There are 2 Bits that control the voltage of VAUX2.
VAUX3
On the A780 VAUX3 is connected to TransFlash power. There are 4 Bits that control the voltage of VAUX3 from 0.6V to 3.6V. Basically the formula is U = 0.6V + (N * 0.2V).
Please note that the voltage can't be set below 1.2V. The exact reason for that behaviour is unknown, but I belive it's because the baseband processor overrides lower voltages on its primary SPI connection to the PPCAP2.
| N | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Voltage U |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0.6V |
| 1 | 0 | 0 | 0 | 1 | 0.8V |
| 2 | 0 | 0 | 1 | 0 | 1.0V |
| 3 | 0 | 0 | 1 | 1 | 1.2V |
| 4 | 0 | 1 | 0 | 0 | 1.4V |
| 5 | 0 | 1 | 0 | 1 | 1.6V |
| 6 | 0 | 1 | 1 | 0 | 1.8V |
| 7 | 0 | 1 | 1 | 1 | 2.0V |
| 8 | 1 | 0 | 0 | 0 | 2.2V |
| 9 | 1 | 0 | 0 | 1 | 2.4V |
| 10 | 1 | 0 | 1 | 0 | 2.6V |
| 11 | 1 | 0 | 1 | 1 | 2.8V |
| 12 | 1 | 1 | 0 | 0 | 3.0V |
| 13 | 1 | 1 | 0 | 1 | 3.2V |
| 14 | 1 | 1 | 1 | 0 | 3.4V |
| 15 | 1 | 1 | 1 | 1 | 3.6V |
Backlight / LED control
The PCAP2 can control two backlights' and two LEDs' brightness via PWM. Each LED PWM can be set to 16 different values via 4 bits and a seperate enable bit. Each backlight PWM can be set to 32 different values via 5 bits.
| Device | Bits in PERIPH register |
|---|---|
| main backlight | [0:4] |
| aux backlight (keylight) | [20:24] |
| red LED | [7:10] enable:[5] |
| green LED | [11:14] enable:[6] |
A/D conversion
The PCAP2 has a 10-Bit A/D-converter. Two groups, each with 7 analog inputs can be multiplexed onto the converter. The ADC functions are controlled via the ADC1 and ADC2 registers.
Registers seperate for each group
| Function | Group 1 | Group 2 | Description |
|---|---|---|---|
| ADD | ADC2[0:9] | ADC2[10:19] | 10 Bit conversion result |
| ADINC | ADC2[20] | ADC2[20] | ??? |
| ADA | ADC1[4:6] | ADC1[7:9] | 3 Bit input select - selects channel for conversion and for readout later |
| AD_SEL | ADC1[2] | ADC1[3] | ??? |
| MTR | ADC1[15] | ADC1[16] | ??? |
| Function | Location | Description |
|---|---|---|
| ADEN | ADC1[0] | enable A/D converter |
| RAND | ADC2[1] | 0=convert entire group 1=convert single channel |
| ATO | ADC1[10:13] | 4 Bit conversion delay |
| ATOX | ADC1[14] | ??? |
| ASC | ADC2[22] | 1=start conversion |
| TS_M | ADC1[17:19] | Touchscreen mode |
| TS_REF_LOWPWR | ADC1[20] | 0=TS reference voltage on 1=TS reference volatage off |
| TS_REFENB | ADC1[21] | ??? |
| BATT_I_POLARITY | ADC1[22] | Battery polarity invert bit |
| BATT_I_ADC | ADC1[23] | Simultaneous read of voltage and current |
Touchscreen modes
| Mode# | Name | Description |
|---|---|---|
| 0 | POSITION_X_MEASUREMENT | ??? |
| 1 | POSITION_XY_MEASUREMENT | ??? |
| 2 | PRESSURE_MEASUREMENT | ??? |
| 3 | PLATE_X_MEASUREMENT | ??? |
| 4 | PLATE_Y_MEASUREMENT | ??? |
| 5 | STANDBY_MODE | ??? |
| 6 | NONTS_MODE | ??? |
Peripheral Control
TODO: Describe pstat bits.
Sound
The PCAP2 deals with everything audio related on the EZX platform. Its connected to AP and BP via SSP. It can play as slave and master (Motorola's kernel uses PCAP as master).
It supports 16 bit mono and stereo audio. It does all the audio routing, between speakers/mic/headphone and ap/bp.
On the E680 there is another amplifier (lm7845) for the boomer, and a MIDI chipset. -- Is this really lm7845?? the entire internet and National's website doesn't list anything for this... "Boomer" is the marketing name for some NS amplifier chips. Listed as I2C capable Boomer chips on NS website are e.g. LM4931, LM4934, LM4936, LM4855, LM4857, LM4859. Could "LM7845" actually be LM4857??? Yup, it most likely is, since one of Stefan's photos shows an IC directly near the audio-related ICs which matches exactly geometry- and package-wise. NO, it dead certainly is!! Witness a nice little untitled E680 image in NS's AudioSystem.pdf file which describes LM4857 mobile applications!! And the LM4857... is being used in the Neo1973!! --> drivers galore!?!?
A780 has a attenuate GPIO to mute audio output and avoid codec power on noise.
PCAP audio clock is feed by the AP 13MHZ clock when using the ST_DAC or BP clock when using the AUD_CODEC.
There are at least 4 registers that are used on audio.
- 0x0b AUD_CODEC BP codec ??
0 audihpf Input high pass filer enable
1 smb Master/Slave select
2 audohpf Output high pass filter enable
3 cd_ts ??????
4 dlm ??????
5 adith ??????
6-8 cdc clk Codec clock config
0 13m0
1 15m36
2 16m8
3 19m44
4 26m0
9 cdc clk inv
10 fs inv
11 df reset Reset codec ??
12 cdc en Enable codec
13 cdc clk en Enable codec clock
14 fs 8k 16k sample rate select
0 8k
1 16k
15 dig aud in
16 clk in sel Clock source select
17 mic2 mux
18-22 mic2ig
23 mic2ig pri adj
24 cdc pri adj
- 0x0c AUD_RX_AMPS Speaker/output mixer
0 a1 en enable earpiece
1 a2 en enable louderspeaker
2-3 unknown
4 a4 en nc?
5 aright en enable headset right
6 aleft en enable headset left
7 cd byp bp codec bypass ????
8 cdc sw telephone switch to right pga ????
0
1 enable telephone
9 st dac sw stereo switch
10 pga in sw clean close pga_inr into pga ????
11 pga r en enable pga right
12 pga l en enable pga left
13-16 audio output gain (crap 16 step mono control for the master volume)
17 a1ctrl
18 unknown
19-20 mono
0 R_L_STEREO stereo
1 RL mono
2 RL 3db
3 RL 6db louderspeaker
21 audog pri adj
22 mono pri adj
23-24 rx pri adj
- 0x0d ST_DAC stereo codec
0 smb st dac
0 bitclk output
1 stdet en
2-4 st clk stereo dac clock config
0 clk in 13m0
1 clk in 15m36
2 clk in 16m8
3 clk in 19m44
4 clk in 26m0
5 clk in ext mclk
6 clk in fsync
7 clk in bitclk
5 clk en enable codec clock
6 df reset st dac codec reset
7 dac en enable dac
8-11 sample rate
0 8k
1 11k
2 12k
3 16k
4 22k
5 24k
6 32k
7 44k
8 48k
9-15 unknown
12 dig aud in st dac used on init audio IO=part1
13-14 dig aud fs
0 audio interface normal pcm
1 audio interface network
2 audio interface i2s
3 unknown
15-16 bclk
0 slot 16
1 slot 8
2 slot 4
3 slot 2
17 st clk inv
18 st fs inv
19 st dac clk in sel Clock source select
20-23 unknown
24 st dac pri adj
- 0x1a TX_AUD_AMPS Mic/input mixer
0-4 audio input gain (32 step volume control for the mic)
5 a3 enable enable headset mic inv
6 a3 mux
7 a5 enable enable handset mic inv
8 a5 mux
9 ext mic mux carkit input
10 mb on2 enable headset mic
11 mb on1 enable handset mic
12 a1id tx
13 a1 config
14 ahs config
15 a2 config
16-18 unknown
19 audio lowpwr
20 audio stby
21 v2 en 2 connected to bp . power bp codec?
22 audig pri adj
23-24 tx pri adj
- PCAP registers dump on 2.4
- Right after boot
ISR 00000000 MSR 0003EDBD PSTAT 002207C0 VREG2 000020AC VREG 00325BD2 BATT_DAC 00200000 ADC1 000A0000 ADC2 00000000 AUD_CODEC 00000007 AUD_RX_AMPS 00034000 AUD_ST_DAC 00059001 BUSCTRL 000002B4 PERIPH 00000000 LOWPWR 00D57103 AUD_TX_AMPS 00200016 GP 00000100
- When playing stereo audio
ISR 00000000 MSR 0003EDBD PSTAT 002207C0 VREG2 000020AC VREG 00325BD2 BATT_DAC 00200000 ADC1 000A01DC ADC2 000FFCEB AUD_CODEC 00010007 AUD_RX_AMPS 001B5A02 AUD_ST_DAC 000D97A0 BUSCTRL 000002B4 PERIPH 00000000 LOWPWR 00D57103 AUD_TX_AMPS 00200016 GP 00000100 <4>Snd driver w20076 <7 DEBUG>: ASSCR0 = 0x1000bf <4>Snd driver w20076 <7 DEBUG>: ASSCR1 = 0x23200100 <4>Snd driver w20076 <7 DEBUG>: ASSPSP = 0x100002 <4>Snd driver w20076 <7 DEBUG>: ASSSR = 0x40f024
- On a call
ISR 00000000 MSR 0003EDBD PSTAT 002207C0 VREG2 000020AC VREG 00325BD2 BATT_DAC 00200000 ADC1 000A01DC ADC2 000FFCBF AUD_CODEC 00003005 AUD_RX_AMPS 0008E901 AUD_ST_DAC 00000000 BUSCTRL 000002B4 PERIPH 00000000 LOWPWR 00D57103 AUD_TX_AMPS 00200910 GP 00000100
- When recording (FIXME)
And at least 2 registers used for routing audio for audio peripherals (USB-EMU and headphone) (todo: describe registers and bits)
I have discovered (by accident) that PCAP is also aware of the BP mode, when BP is in flash mode, PCAP will interrupt AP with ONOFFI, this doesnt happen when BP is in normal mode.
